This invention relates to programmable logic arrays, and more particularly to static programmable logic arrays.
Programmable logic arrays, also known as PLAs, comprise an array of logical AND and OR gates which is programmed for specific functions. Each output function is the sum (logical OR) of selected products (logical AND) of the inputs. In CMOS technology, the AND plane is implemented as a NOR array with inverted inputs, and the OR plane is implemented as a NOR array with inverted outputs. PLAs are useful in implementing a variety of functions, including random logic networks, data routing, code conversion, instruction decoding, and state sequences.
Programmable logic arrays include the static, precharged, and dynamic types. Static PLAs are able to maintain charge on the internal nodes; several designs are described below. The precharge and dynamic PLAs must be provided with external precharge and evaluate signals. Generally, precharge and dynamic PLAs also require that the precharge or clock signal be provided at a certain minimum frequency to maintain charge on the internal nodes.
In order to avoid DC power dissipation, the NOR array of the static type of PLA has been designed either as a fully complementary array or, more commonly, as a complementary NMOS array with cross coupled PMOS pullup transistors. In fully complementary designs, each branch of the NOR array comprises a NMOS section and a PMOS section, one of which being a parallel circuit while the other a series circuit. FIG. 1 is an example of a typical branch of a NOR array comprising NMOS parallel circuit section 10 and PMOS series circuit section 12. When any one or more of the NMOS transistors in the parallel section 10 are ON and pulling the output 13 to logical zero, the corresponding PMOS transistor or transistors in the PMOS series section 12 are OFF, thereby preventing DC current draw. This design approach has several drawbacks. The size of the NOR array is large, as two full MOS arrays are required. The performance of the NOR array deteriorates with increasing size, and the functionality cannot be guaranteed. Moreover, the reliability of the NOR array is difficult to ensure, due to the large number of devices in the design.
In complementary NMOS array designs, NOR circuit 14 and its complementary tree 16 are implemented with NMOS transistors, and cross-coupled PMOS pullup transistors 18 and 20 are used at the top of the arrays. When any one or more of the transistors in the parallel circuit 14 is ON and pulling the output 21 to logical zero, the corresponding transistor or transistors in the series section 16 are OFF. As a result, PMOS transistor 18 turns ON and PMOS transistor 20 turns OFF, preventing DC power draw through circuit 14. When all transistors in the parallel circuit 14 are OFF, all the transistors in the series circuit 16 are ON and pull down the gate of the PMOS transistor 20, which turns ON. As a result, PMOS transistor 18 turns, preventing DC power draw through circuit 16. Unfortunately, this design approach also has several drawbacks. The size of the array is large, mostly due to the sizing of the series NMOS transistors. Reliability is difficult to ensure because the number of busses in the NOR array is doubled. Moreover, functionality cannot be guaranteed independently of array size.
While other proposals have been made to overcome the disadvantages of the fully complementary and complementary NMOS designs, they do so at the expense of significant DC power dissipation. In one such design, known as a pseudo-NMOS static CMOS PLA, PMOS pullup transistors having their gates tied to ground are used on the NMOS array lines. While this approach results in a static PLA, the PMOS pullup transistors are essentially resistive pullups and dissipate a significant amount of DC power.